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FEATURES 256 Position Multiple Independently Programmable Channels AD5204--4-Channel AD5206--6-Channel Potentiometer Replacement 10 k , 50 k , 100 k 3-Wire SPI-Compatible Serial Data Input +2.7 V to +5.5 V Single Supply; 2.7 V Dual Supply Operation Power ON Midscale Preset APPLICATIONS Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching
CS CLK
4-/6-Channel Digital Potentiometers AD5204/AD5206
FUNCTIONAL BLOCK DIAGRAMS AD5204
EN A2 A1 A0 D7 ADDR DEC D0 D7 RDAC LATCH #1 R VDD A1 W1 B1
SDO
DO
SER REG D7 SDI DI D0 8 POWERON PRESET RDAC LATCH #4 D0 R A4 W4 B4 SHDN VSS PR
GND
GENERAL DESCRIPTION
The AD5204/AD5206 provides four-/six-channel, 256 position digitally-controlled Variable Resistor (VR) devices. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. Each channel of the AD5204/ AD5206 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI-compatible serial-input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. The variable resistor offers a completely programmable value of resistance between the A terminal and the wiper or the B Terminal and the wiper. The fixed A-to-B terminal resistance of 10 k, 50 k, or 100 k has a nominal temperature coefficient of 700 ppm/C. Each VR has its own VR latch which holds its programmed resistance value. These VR latches are updated from an internal serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Eleven data bits make up the data word clocked into the serial input register. The first three bits are decoded to determine which VR latch will be loaded with the last eight bits of the data word when the CS strobe is returned to logic high. A serial data output pin at the opposite end of the serial register (AD5204 only) allows simple daisy-chaining in multiple VR applications without additional external decoding logic.
CS CLK EN A2 A1 A0 D7 ADDR DEC D0 D7
AD5206
VDD A1 W1
RDAC LATCH #1 R
B1
SER REG D7 SDI DI D0 8 POWERON PRESET D0 RDAC LATCH #6 R VSS A6 W6 B6
GND
An optional reset (PR) pin forces all the AD5204 wipers to the midscale position by loading 80H into the VR latch. The AD5204/AD5206 is available in both surface mount (SOL-24), TSSOP-24 and the 24-lead plastic DIP package. All parts are guaranteed to operate over the extended industrial temperature range of -40C to +85C. For additional single, dual, and quad channel devices, see the AD8400/AD8402/ AD8403 products.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
ELECTRICAL CHARACTERISTICS unless otherwise noted.)
Parameter Symbol Conditions
AD5204/AD5206-SPECIFICATIONSor +3 V (V = +5 V 10%
DD
10%, VSS = 0 V, VA = +VDD, VB = 0 V, -40 C < TA < +85 C
Min -1 -2 -30 Typ1 1/4 1/2 700 0.25 50 8 -1 -2 -2 0 VSS Max +1 +2 +30 1.5 100 Units LSB LSB % ppm/C % Bits LSB LSB ppm/C LSB LSB V pF pF A nA V V V V A pF V V A A mW %/% kHz kHz kHz % s nV/Hz ns ns ns ns ns ns ns ns ns ns
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential NL 2 R-DNL RWB , VA = No Connect R-INL RWB , VA = No Connect Resistor Nonlinearity Error2 RAB TA = +25C Nominal Resistor Tolerance 3 VAB = V DD, Wiper = No Connect Resistance Temperature Coefficient RAB/T CH1 to 2, 3, 4, or 5, 6; VAB = V DD Nominal Resistance Match R/RAB Wiper Resistance RW IW = 1 V/R, VDD = +5 V DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs Resolution N DNL Differential Nonlinearity 4 INL Integral Nonlinearity 4 Code = 40H Voltage Divider Temperature Coefficient VW/T Code = 7FH Full-Scale Error VWFSE Zero-Scale Error VWZSE Code = 00H RESISTOR TERMINALS Voltage Range5 Capacitance6 Ax, Bx Capacitance6 Wx Shutdown Current 7 Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Output Logic High Output Logic Low Input Current Input Capacitance6 POWER SUPPLIES Power Single Supply Range Power Dual Supply Range Positive Supply Current Negative Supply Current Power Dissipation 8 Power Supply Sensitivity DYNAMIC CHARACTERISTICS Bandwidth -3 dB
6, 9
1/4 1/2 15 -1 +1
+1 +2 0 +2 VDD
VA, VB, VW CA, C B CW IA_SD ICM VIH VIL VOH VOL IIL CIL VDD Range VDD/SS Range IDD ISS PDISS PSS BW_10K BW_50K BW_100K THDW tS e N_WB
f = 1 MHz, Measured to GND, Code = 40H f = 1 MHz, Measured to GND, Code = 40H VA = VB = VW = 0, VDD = +2.7 V, VSS = -2.5 V VDD = +5 V/+3 V VDD = +5 V/+3 V RPULL-UP = 1 k to +5 V IOL = 1.6 mA, VLOGIC = +5 V VIN = 0 V or +5 V 2.4/2.1
45 60 0.01 1
5
0.8/0.6 4.9 0.4 1 5
VSS = 0 V VIH = +5 V or V IL = 0 V VSS = -2.5 V, VDD = +2.7 V VIH = +5 V or V IL = 0 V VDD = +5 V 10% RAB = 10 k RAB = 50 k RAB = 100 k VA = 1.414 V rms, V B = 0 V dc, f = 1 kHz VA = 5 V, VB = 0 V, 1 LSB Error Band RWB = 5 k, f = 1 kHz, PR = 0
2.7 2.3 12 12 0.0002 721 137 69 0.004 2/9/18 9 20 5 5 1 15 40 90 0 0 10
5.5 2.7 60 60 0.3 0.005
Total Harmonic Distortion VW Settling Time (10K/50K/100K) Resistor Noise Voltage
INTERFACE TIMING CHARACTERISTICS Applies to All Parts 6, 10 Input Clock Pulsewidth tCH , tCL Clock Level High or Low Data Setup Time tDS Data Hold Time tDH tPD RL = 2 k, CL < 20 pF CLK to SDO Propagation Delay11 CS Setup Time tCSS CS High Pulsewidth tCSW Reset Pulsewidth tRS CLK Fall to CS Fall Setup tCSH0 CLK Fall to CS Rise Hold Time tCSH1 CS Rise to Clock Rise Setup tCS1
NOTES
1 2
150
Typicals represent average readings at +25C and VDD = +5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 23 test circuit. I W = VDD/R for both VDD = +3 V or VDD = +5 V. 3 VAB = V DD, Wiper (VW ) = No connect. 4 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and V B = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 22 test circuit.
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Resistor Terminals A, B, W, have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test. 7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode. 8 PDISS is calculated from (I DD x V DD). CMOS logic level inputs result in minimum power dissipation. 9 All dynamic characteristics use V DD = +5 V. 10 See timing diagrams for location of measured values. All input control voltages are specified with t R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V DD = +3 V or +5 V. 11 Propagation delay depends on value of V DD, R L and C L. See Operation section.
6 5
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +7 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, -7 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V VA, VB, V W to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS , VDD Ax-Bx, Ax-Wx, Bx-Wx . . . . . . . . . . . . . . . . . . . . . . 20 mA Digital Input and Output Voltage to GND . . . . . . . 0 V, +7 V Operating Temperature Range . . . . . . . . . . . -40C to +85C Maximum Junction Temperature (TJ MAX) . . . . . . . . +150C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300C
Package Power Dissipation . . . . . . . . . . . . . . (T J max-TA)/JA Thermal Resistance JA P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63C/W SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143C/W
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5204/AD5206 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD5204/AD5206
1 SDI 0 1 CLK 0 1 CS 0 VOUT VDD 0V RDAC LATCH LOAD VOUT 0V 1 LSB ERROR BAND A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 PR 0 VDD 1
tRS
tS
1 LSB
Figure 3. AD5204 Preset Timing Diagram Figure 1. Timing Diagram
SDI (DATA IN)
1 Ax OR Dx 0 Ax OR Dx
tDS
SDO (DATA OUT) 1 Ax OR Dx 0 Ax OR Dx
tDH
tCH
1 CLK 0 1 0
tPD_MAX tCS1 tCL tCSH1 tCSW tS
tCSH0 tCSS
CS
VOUT
VDD 0V 1 LSB ERROR BAND
1 LSB
Figure 2. Detail Timing Diagram
ORDERING GUIDE
Model
AD5204BN10 AD5204BR10 AD5204BRU10 AD5204BN50 AD5204BR50 AD5204BRU50 AD5204BN100 AD5204BR100 AD5204BRU100 AD5206BN10 AD5206BR10 AD5206BRU10 AD5206BN50 AD5206BR50 AD5206BRU50 AD5206BN100 AD5206BR100 AD5206BRU100
k
10 10 10 50 50 50 100 100 100 10 10 10 50 50 50 100 100 100
Temperature Range
-40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Descriptions
24-Lead Narrow Body (PDIP) 24-Lead Wide Body (SOIC) 24-Lead Thin Shrink SO Package (TSSOP) 24-Lead Narrow Body (PDIP) 24-Lead Wide Body (SOIC) 24-Lead Thin Shrink SO Package (TSSOP) 24-Lead Narrow Body (PDIP) 24-Lead Wide Body (SOIC) 24-Lead Thin Shrink SO Package (TSSOP) 24-Lead Narrow Body (PDIP) 24-Lead Wide Body (SOIC) 24-Lead Thin Shrink SO Package (TSSOP) 24-Lead Narrow Body (PDIP) 24-Lead Wide Body (SOIC) 24-Lead Thin Shrink SO Package (TSSOP) 24-Lead Narrow Body (PDIP) 24-Lead Wide Body (SOIC) 24-Lead Thin Shrink SO Package (TSSOP)
Package Options
N-24 R-24/SOL-24 RU-24 N-24 R-24/SOL-24 RU-24 N-24 R-24/SOL-24 RU-24 N-24 R-24/SOL-24 RU-24 N-24 R-24/SOL-24 RU-24 N-24 R-24/SOL-24 RU-24
The AD5204/AD5206 contains 5,925 transistors. Die size; 92 mil x 114 mil, 10,488 sq. mil.
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AD5204 PIN CONFIGURATION AD5206 PIN CONFIGURATION
NC 1 NC 2 GND 3 CS 4 PR 5 VDD 6 SHDN 7 SDI
8
24 23 22 21 20
B4 W4 A4 B2 W2 A2 A1 W1 B1 A3 W3 B3
A6 1 W6 2 B6 3 GND 4 CS 5 VDD 6 SDI 7 CLK 8 VSS 9 B5 10 W5 11 A5 12
24 23 22 21 20
B4 W4 A4 B2 W2 A2 A1 W1 B1 A3 W3 B3
AD5204
(NOT TO SCALE)
19 18 17 16 15 14 13
AD5206
(NOT TO SCALE)
19 18 17 16 15 14 13
CLK 9 SDO 10 VSS 11 NC 12
NC = NO CONNECT
AD5204 PIN FUNCTION DESCRIPTIONS
AD5206 PIN FUNCTION DESCRIPTIONS
Pin No. 1, 2, 12 3 4
Name NC GND CS
Description Not Connected. Ground. Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded based on the address bits and loaded into the target RDAC latch. Active low preset to midscale; sets RDAC registers to 80H. Positive power supply, specified for operation at both +3 V or +5 V. (Sum of |VDD| + |VSS| <5.5 V.) Active low input. Terminal A open-circuit. Shutdown controls Variable Resistors #1 through #4. Serial Data Input. MSB First. Serial Clock Input, positive edge triggered. Serial Data Output, Open Drain transistor requires pull-up resistor. Negative Power Supply, specified for operation at both 0 V or -2.7 V. (Sum of |VDD| + |VSS| <5.5 V.) B Terminal RDAC #3. Wiper RDAC #3, addr = 0102. A Terminal RDAC #3. B Terminal RDAC #1. Wiper RDAC #1, addr = 0002. A Terminal RDAC #1. A Terminal RDAC #2. Wiper RDAC #2, addr = 0012. B Terminal RDAC #2. A Terminal RDAC #4. Wiper RDAC #4, addr = 0112. B Terminal RDAC #4.
Pin No. 1 2 3 4 5
Name A6 W6 B6 GND CS
Description A Terminal RDAC #6. Wiper RDAC #6, addr = 1012. B Terminal RDAC #6. Ground. Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded based on the address bits and loaded into the target RDAC latch. Positive power supply, specified for operation at both +3 V or +5 V. (Sum of |VDD| + |VSS| <5.5 V.) Serial Data Input. MSB First. Serial Clock Input, positive edge triggered. Negative Power Supply, specified for operation at both 0 V or -2.7 V. (Sum of |VDD| + |VSS| <5.5 V.) B Terminal RDAC #5. Wiper RDAC #5, addr = 1002. A Terminal RDAC #5. B Terminal RDAC #3. Wiper RDAC #3, addr = 0102. A Terminal RDAC #3. B Terminal RDAC #1. Wiper RDAC #1, addr = 0002. A Terminal RDAC #1. A Terminal RDAC #2. Wiper RDAC #2, addr = 0012. B Terminal RDAC #2. A Terminal RDAC #4. Wiper RDAC #4, addr = 0112. B Terminal RDAC #4.
5 6
PR VDD SHDN
6
VDD
7
7 8 9
SDI CLK VSS
8 9 10 11
SDI CLK SDO VSS
13 14 15 16 17 18 19 20 21 22 23 24
B3 W3 A3 B1 W1 A1 A2 W2 B2 A4 W4 B4
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
B5 W5 A5 B3 W3 A3 B1 W1 A1 A2 W2 B2 A4 W4 B4
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AD5204/AD5206-Typical Performance Characteristics
120 110 VDD/VSS = 2.7V/0V 100 NORMALIZED GAIN - dB SWITCH RESISTANCE - 90 80 70 VDD/VSS = 5.5V/0V 60 50 40 30 -3.0 VDD/VSS = 2.7V 0 -2 -4 VDD = 2.7V VSS = -2.7V VA = 100mV rms DATA = 80H VA 100k OP42 10k
50k
-2.0
-1.0
0 1.0 2.0 3.0 COMMON MODE - V
4.0
5.0
6.0
1k
10k 100k FREQUENCY - Hz
1M
Figure 4. Incremental Wiper ON Resistance vs. Voltage
Figure 7. -3 dB Bandwidth vs. Terminal Resistance, 2.7 V Dual Supply Operation
0 -6 -12 -18 DATA = 80H DATA = 40H DATA = 20H DATA = 10H DATA = 08H DATA = 04H -36 DATA = 02H -42 -48 DATA = 01H VDD = 2.7V VSS = -2.7V VA = 100mV rms TA = +25 C VA OP42 10k 100k FREQUENCY - Hz 1M
-5.99 -6.00 -6.01 -6.02 10k -6.03 GAIN - dB -6.04 -6.05 -6.06 -6.07 OP42 -6.08 -6.09 100 VB = 0V 1k 10k FREQUENCY - Hz 100k VDD = 2.7V VSS = -2.7V VA = 100mV rms DATA = 80H TA = +25 C VA 50k 100k GAIN - dB
-24 -30
-54 -60 1k
Figure 5. Gain Flatness vs. Frequency
Figure 8. Bandwidth vs. Code, 10K Version
0 -6 -12 NORMALIZED GAIN - dB 0 -2 -4 VDD = 2.7V VSS = 0V VA = 100mV rms DATA = 80H TA = +25 C 2.7V 100k -42 OP42 +1.5V -48 -54 10k 100k FREQUENCY - Hz 1M -60 1k 10k -18 -24 GAIN - dB -30 -36 DATA = 80H DATA = 40H DATA = 20H DATA = 10H DATA = 08H DATA = 04H DATA = 02H DATA = 01H
VDD = 2.7V VSS = -2.7V VA = 100mV rms TA = +25 C VA OP42
50k
1k
10k 100k FREQUENCY - Hz
1M
Figure 6. -3 dB Bandwidth vs. Terminal Resistance, 2.7 V Single Supply Operation
Figure 9. Bandwidth vs. Code, 50K Version
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0 -6 -12 -18 -24 GAIN - dB -30 -36 -42 -48 -54 -60 1k DATA = 80H DATA = 40H SUPPLY CURRENT - mA DATA = 20H DATA = 10H DATA = 08H DATA = 04H DATA = 02H DATA = 01H
VDD = 2.7V VSS = -2.7V VA = 100mV rms TA = +25 C VA
8 TA = +25 C 7 6 5 4 3 2 1
OP42
IDD, VDD/VSS = 5.5V/0V, DATA = 55H ISS, VDD/VSS = 2.7V, DATA = 55H
IDD, VDD/VSS = 5,5V/0V, DATA = FFH ISS, VDD/VSS = 2.7V, DATA = FFH
IDD, VDD/VSS = 2.7V/0V, DATA = FFH IDD, VDD/VSS = 2.7V/0V, DATA = 55H
10k 100k FREQUENCY - Hz
1M
0 10k
100k 1M FREQUENCY - Hz
10M
Figure 10. Bandwidth vs. Code, 100K Version
Figure 13. Supply Current vs. Clock Frequency
2.5
60 TA = +25 C
2.0
50 VSS = -3.0V 40 VDD = 5.0V 10% 10%
TRIP POINT - V
DUAL SUPPLY VSS = 0V
PSRR - dB
1.0
SINGLE SUPPLY VDD = VSS
30 VDD = 3.0V 20 10%
0.1
0.5
10
0.0 1.0
2.0
3.0 4.0 5.0 SUPPLY VOLTAGE VDD - Volts
6.0
0 10
100
1k FREQUENCY - Hz
10k
100k
Figure 11. Digital Input Trip Point vs. Supply Voltage
Figure 14. Power Supply Rejection vs. Frequency
100
ISS AT VDD/VSS =
2.7V
1.0
TA = +25 C
VDD = +2.7V VSS = -2.7V TA = +25 C RAB = 10k
10 SUPPLY CURRENT - mA
0.1
1 IDD AT VDD/VSS = 0.1 2.7V
THD + NOISE - %
IDD AT VDD/VSS = 5.5V/0V
0.01 NONINVERTING TEST CIRCUIT
0.001
0.01 IDD AT VDD/VSS = 2.7V/0V 0.001 0 1 2 3 4 5 INCREMENTAL INPUT LOGIC VOLTAGE - Volts 6
0.0001 10
INVERTING TEST CIRCUIT
100
1k FREQUENCY - Hz
10k
100k
Figure 12. Supply Current vs. Input Logic Voltage
Figure 15. Total Harmonic Distortion Plus Noise vs. Frequency
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OPERATION
The AD5204/AD5206 provides a four-/six-channel, 256-position digitally-controlled variable resistor (VR) device. Changing the programmed VR settings is accomplished by clocking in a 11bit serial data word into the SDI (Serial Data Input) pin. The format of this data word is three address bits, MSB first, followed by eight data bits, MSB first. Table I provides the serial register data word format.
Table I. Serial-Data Word Format
data 00H . This B terminal connection has a wiper contact resistance of 45 . The second connection (10 k part) is the first tap point located at 84 [= RBA (nominal resistance)/256 + RW = 84 + 45 ] for data 01 H. The third connection is the next tap point representing 78 + 45 = 123 for data 02H. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10006 . The wiper does not directly connect to the A terminal. See Figure 16 for a simplified diagram of the equivalent RDAC circuit. The general transfer equation determining the digitally programmed output resistance between Wx and Bx is:
ADDR B10 B9 B8 A2 A1 MSB 210 A0 LSB 28
DATA B7 B6 D7 D6 MSB 27
B5 D5
B4 D4
B3 D3
B2 D2
B1 D1
B0 D0 LSB 20
R WB (Dx) = (Dx)/256 x R BA + R W
(1)
where Dx is the data contained in the 8-bit RDACx latch, and RBA is the nominal end-to-end resistance. For example, when VB = 0 V and A terminal is open-circuit, the following output resistance values will be set for the following RDAC latch codes (applies to the 10K potentiometer):
Table II.
See Table IV for the AD5204/AD5206 address assignments to decode the location of VR latch receiving the serial register data in Bits B7 through B0. VR outputs can be changed one at a time in random sequence. The AD5204 presets to a midscale by asserting the PR pin, simplifying fault condition recovery at power up. Both parts have an internal power ON preset that places the wiper in a preset midscale condition at power ON. In addition, the AD5204 contains a power shutdown SHDN pin which places the RDAC in a zero power consumption state where Terminals Ax are open circuited and the wiper Wx is connected to Bx resulting in only leakage currents being consumed in the VR structure. In shutdown mode the VR latch settings are maintained, so that, returning to operational mode from power shutdown, the VR settings return to their previous resistance values.
RS Ax
D (DEC) 255 128 1 0
RWB10006 5045 84 45
Output State Full Scale Midscale (PR = 0 Condition) 1 LSB Zero Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of 45 is present. Care should be taken to limit the current flow between W and B in this state to a maximum value of 20 mA to avoid degradation or possible destruction of the internal switch contact. Like the mechanical potentiometer the RDAC replaces, it is totally symmetrical. The resistance between the Wiper W and Terminal A produces a digitally controlled resistance RWA. When these terminals are used the B terminal should be tied to the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general transfer equation for this operation is: R WA (Dx) = (256-Dx)/256 x R BA + R W (2) where Dx is the data contained in the 8-bit RDACx latch, and RBA is the nominal end-to-end resistance. For example, when VA = 0 V and B terminal is tied to the Wiper W the following output resistance values will be set for the following RDAC latch codes:
Table III.
SHDN
D7 D6 D5 D4 D3 D2 D1 D0 RDAC LATCH & DECODER
RS
RS
Wx
RS
Bx
Figure 16. AD5204/AD5206 Equivalent RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation
D (DEC) 255 128 1 0
RWA84 5045 10006 10045
Output State Full Scale Midscale (PR = 0 Condition) 1 LSB Zero Scale
The nominal resistance of the RDAC between Terminals A and B are available with values of 10 k, 50 k and 100 k. The last digits of the part number determine the nominal resistance value, e.g., 10 k = 10; 100 k = 100. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal, plus the B terminal contact. The eight-bit data word in the RDAC latch is decoded to select one of the 256 possible settings. The wiper's first connection starts at the B terminal for -8-
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The typical distribution of RBA from channel-to-channel matches within 1%. However, device-to-device matching is process lot dependent, having a 30% variation. The change in RBA with temperature has a 700 ppm/C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation
The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example, connecting A terminal to +5 V and B terminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to 1 LSB less than +5 V. Each LSB of voltage is equal to the voltage applied across Terminal AB divided by the 256-position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to terminals AB is: VW (Dx) = Dx/256 x VAB + VB (3) Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors not the absolute value, therefore, the drift improves to 15 ppm/C.
CS CLK EN A2 A1 DO A0 D7 ADDR DEC D0
transfer data to the next package's SDI pin. The pull-up resistor termination voltage may be larger than the VDD supply of the AD5204 SDO output device, e.g., the AD5204 could operate at VDD = 3.3 V and the pull-up for interface to the next device could be set at +5 V. This allows for daisy chaining several RDACs from a single processor serial-data line. Clock period needs to be increased when using a pull-up resistor to the SDI pin of the following device in the series. Capacitive loading at the daisy chain node SDO-SDI between devices must be accounted for to successfully transfer data. When daisy chaining is used, the CS should be kept low until all the bits of every package are clocked into their respective serial registers insuring that the address bits and data bits are in the proper decoding location. This would require 22 bits of address and data complying to the word format provided in Table I if two AD5204 fourchannel RDACs are daisy chained. During shutdown (SHDN) the SDO output pin is forced to the off (logic high state) to disable power dissipation in the pull-up resistor. See Figure 19 for equivalent SDO output circuit schematic.
Table IV. Input Logic Control Truth Table
CLK CS PR SHDN Register Activity L P L L H H H H No SR effect, enables SDO pin. Shift one bit in from the SDI pin. The eleventh previously entered bit is shifted out of the SDO pin. Load SR data into RDAC latch based on A2, A1, A0 decode (Table V). No Operation. Sets all RDAC latches to midscale, wiper centered and SDO latch cleared. Latches all RDAC latches to 80H . Open circuits all Resistor A terminals, connects W to B, turns off SDO output transistor.
AD5204/AD5206
D7 RDAC LATCH #1 R
VDD A1 W1 B1
X X X
P H X
H H L
H H H
SDO (AD5204 ONLY)
SER REG D7 SDI DI D0 D0 RDAC LATCH #4/#6 8 SHDN (AD5204 ONLY) R A4/A6 W4/W6 B4/B6
X X
H H
P H
H L
NOTE: P = positive edge, X = don't care, SR = shift register.
PR (AD5204 ONLY)
GND
Table V. Address Decode Table
Figure 17. Block Diagram
DIGITAL INTERFACING
A2 0 0 0 0 1 1
A1 0 0 1 1 0 0
A0 0 1 0 1 0 1
Latch Decoded RDAC#1 RDAC#2 RDAC#3 RDAC#4 RDAC#5 AD5206 Only RDAC#6 AD5206 Only
The AD5204/AD5206 contain a standard three-wire serial input control interface. The three inputs are clock (CLK), CS and serial data input (SDI). The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation they should be debounced by a flip-flop or other suitable means. Figure 17 shows more detail of the internal digital circuitry. When CS is taken active low the clock loads data into the serial register on each positive clock edge, see Table IV. When using a positive (VDD ) and negative (VSS) supply voltage, the logic levels are still referenced to digital ground (GND). The serial-data-output (SDO) pin contains an open drain nchannel FET. This output requires a pull-up resistor in order to
The data setup and data hold times in the specification table determine the data valid time requirements. The last 11 bits of the data word entered into the serial register are held when CS returns high. At the same time CS goes high it gates the address decoder enabling one of four or six positive edge triggered RDAC latches, see Figure 18 detail.
REV. 0
-9-
AD5204/AD5206
AD5204/AD5206
CS ADDR DECODE RDAC 1 RDAC 2 RDAC 4/6 CLK SDI SERIAL REGISTER V+ IMS DUT A W B VMS IW = 1V/RNOMINAL VW V+ VDD V W2 -[VW1 + IW (R AWII RBW)] RW = -------------------------- IW WHERE VW1 = VMS WHEN IW = 0 AND VW2 = VMS WHEN IW = 1/R
Figure 18. Equivalent Input Control Logic
Figure 24. Wiper Resistance Test Circuit
VA V+ = VDD 10% V+
MS ( ----- ) V DD
The target RDAC latch is loaded with the last eight bits of the serial data word completing one DAC update. Four separate 8bit data words must be clocked in to change all four VR settings.
SHDN CS SDI SERIAL REGISTER D Q GND SDO
~
VDD
A B
V
W VMS
PSRR (dB) = 20 LOG VMS% PSS (%/%) = ------- VDD%
CK RS CLK PR
Figure 25. Power Supply Sensitivity Test Circuit (PSS, PSRR)
A DUT B +5V VIN OFFSET GND W
Figure 19. Detail SDO Output Schematic of the AD5204
All digital pins are protected with a series input resistor and parallel Zener ESD structure shown in Figure 20. Applies to digital pins CS, SDI, SDO, PR, SHDN, CLK
340k LOGIC VSS
OP279
VOUT
+
OFFSET BIAS
Figure 26. Inverting Programmable Gain Test Circuit
+5V
Figure 20. ESD Protection of Digital Pins
OP279
VIN A, B, W OFFSET GND VSS A W DUT B VOUT
OFFSET BIAS
Figure 21. ESD Protection of Resistor Terminals
DUT A V+ B W VMS V+ = VDD 1LSB = V+/256
Figure 27. Noninverting Programmable Gain Test Circuit
A VIN OFFSET GND W DUT B 2.5V +15V
+
OP42
VOUT
Figure 22. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL)
NO CONNECT DUT A W B VMS IW
-15V
Figure 28. Gain vs. Frequency Test Circuit
DUT W B ISW VSS TO VDD RSW = 0.1V ISW CODE = OOH + 0.1V
Figure 23. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
Figure 29. Incremental ON Resistance Test Circuit
-10-
REV. 0
AD5204/AD5206
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Narrow Body PDIP (N-24)
1.275 (32.30) 1.125 (28.60)
24 1 13 12
0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204)
PIN 1 0.210 (5.33) MAX 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.070 (1.77) SEATING 0.045 (1.15) PLANE
24-Lead SOIC (R-24/SOL-24)
0.6141 (15.60) 0.5985 (15.20)
24
13
0.2992 (7.60) 0.2914 (7.40)
1 12
0.4193 (10.65) 0.3937 (10.00)
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) 0.0098 (0.25)
45
0.0118 (0.30) 0.0500 0.0040 (0.10) (1.27) BSC
8 0 0.0192 (0.49) SEATING 0.0125 (0.32) PLANE 0.0138 (0.35) 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
24-Lead Thin Shrink SO Package (TSSOP) (RU-24)
0.311 (7.90) 0.303 (7.70)
24
13
0.256 (6.50) 0.246 (6.25)
1 12
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
0.028 (0.70) 0.020 (0.50)
REV. 0
-11-
PRINTED IN U.S.A.
0.177 (4.50) 0.169 (4.30)
C3677-8-9/99

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